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  to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? 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mos integrated circuit mc-10118b multimedia processor for mobile applications document no. r19ds0008ej0700 (7th edition) (s19657ej7v0ds00) date published march 2010 printed in japan data sheet 2010 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. description emma mobile1-d512 (em1-d512) (sip: mc-10118b) is a multimedia processor for m obile applications that integrates a logic chip incorporating a cpu and dsp, and a mobile ddr sdram chip, in one package. as multimedia processor functions, em1- d512 incorporates one cpu (arm1176jzf-s tm ) and one dsp (spxk701), achieving high-speed, powe r-efficient application processing. em1-d512 also incorporates image processors with various functions to accelerate image processing. various power save modes enable the power to be contro lled according to application processing. moreover, power consumption can be reduc ed during standby by using sequenc es independent from the system. features ? cpu: arm1176jzf-s (max. 500 mhz, i- cache: 32 kb, d-cache: 32 kb) ? dsp: spxk701 (max. 500 mhz, i-ca che: 32 kb, d-cache: 32 kb) ? mobile ddr sdram (512mb) ? dma controller: memory ? memory and memory ? peripheral interface ? timers: general-purpose timers, watchdog timer (wdt) ? image processing ? image processor (resizi ng, filtering, etc.) ? image rotator (0 ?, 90 ?, 180 ?, 270 ?) ? graphics dma (rop and fill) ? image composer (lcd output image synthesis) ? h.264/mpeg-4 avc accelerator application performance ? h.264/mpeg-4 avc enc ode/decode: d1 30 fps ? peripheral interfaces ? memory interface: external bus interface (16 bits: flash memory, etc.), nand interface ? serial interfaces: uart, i2c, audio/voice, spi, irda ? sd card interface ? image-related interfaces: lcd interface, terrestrial digital tv interface (dtv), itu-r.bt656 interface (nts), camera interface ? general-purpose i/o interface ? usb interface ? power supply voltage ? core power supply : v (1.2 v system : 1.1v - 1.3v) ? io power supply : vio18 (1.8 v system : 1.7v - 1.9v), vio3 (3 v system : 2.7v - 3.6v)
mc-10118b data sheet r19ds0008ej0700 2 order information order name package MC-10118BF1-ENY-A 481-pin fpbga (12.7mm 12.7mm)
mc-10118b data sheet r19ds0008ej0700 3 related documents the functions of the multim edia processor for mobile applications are described in the following documents. refer to these documents together with this data sheet during design operations. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? multimedia processor for mobile applications user?s manual audio/voice and pwm interfaces (r19uh0027ej) ddr sdram interface (r19uh0028ej) dma controller (s19255e) i2c interface (s19256e) itu-r bt.656 interface (s19257e) lcd controller (s19258e) microwire (s19259e) nand flash interface (s19260e) spi (s19261e) uart interface (s19262e) image composer (s19263e) image processor unit (s19264e) system control/general-purpos e i/o interface (r19uh0029ej) timer (s19266e) terrestrial digital tv interface (s19267e) camera interface (s19285e) usb interface (s19359e) sd memory card interface (s19361e) pdma (s19373e) one chip (r19uh0030ej) caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing.
mc-10118b data sheet r19ds0008ej0700 4 block diagram emmc sd arm1176 500mhz dsp k701 500mhz video engine sdram if ddr 166m 512mbit wifi em1-logic blue tooth 1-seg nand/ emmc if nand audio dac lcd fm tuner g p s mic async if nor jair o ntsc if usb2.0 hs link i2c spi sd/mmc sdio uart uart uart spi gpio lcd if i2s i2s ofdm if dma pmu int timer*14 ipu rotator ntsc dec em1-d512 cam if
mc-10118b data sheet r19ds0008ej0700 5 pin layout 481-pin fine-pitch bga package (12.7 ? 12.7 mm) 23 21 19 17 15 13 11 9 7 5 3 1 24 22 20 18 16 14 12 10 8 6 4 2 ac aa w u r n l j g e c a ad ab y v t p m k h f d b index mark  top view   bottom view 
mc-10118b data sheet r19ds0008ej0700 6 pin assignment (1/5) pin no. type pin name pin no. type pin name pin no. type pin name a1  g b15 g d5 d urt0_ctsb a2  g b16 d jt0_tms d6  g a3  g b17 a det1 d7 vio3 a4 d pwm0 b18 j lcd_hsync d8 d sp0_so a5 d urt0_srin b19  g d9 d pm0_sen a6  g b20  v d10 c iic_scl a7  v b21  vio18 d11  va1 a8 c pm0_clk b22 j lcd_g1 d12 e bootsel2 a9 b c32k b23  g d13 d gio_p3 a10  va2 b24  g d14 vio3 a11  g c1  g d15  g a12  va3 c2 d dtv_data d16 d jt0_tdo a13  v c3 d urt2_srin d17 c jt0_trstb a14  vio3 c4 d urt2_rtsb d18 j lcd_enable a15  g c5 d urt0_rtsb d19 j lcd_b4 a16 d refclko c6  g d20 j lcd_b1 a17 z osc12m_cko c7  vio3 d21 j lcd_g4 a18 z osc12m_cki c8 d sp0_si d22 j lcd_r5 a19  g c9 c iic2_scl d23 j lcd_r4 a20  v c10 c iic_sda d24 j lcd_pxclk a21  vio18 c11  va1 e1  v a22  g c12 e bootsel1 e2  v a23  g c13 d gio_p2 e3  vio18 a24  g c14 vio3 e4  vio18 b1  g c15 g e5 d gio_p6 b2  g c16 d jt0_tdi e6 d gio_p5 b3 d urt2_sout c17 d jt0_rtck e7 d gio_p4 b4 d pwm1 c18 j lcd_vsync e8 d sp0_cs2 b5 d urt0_sout c19 j lcd_b3 e9 d sp0_cs0 b6 g c20 j lcd_b0 e10 d pm0_si b7 v c21 j lcd_g3 e11 r te2 b8 d sp0_clk c22 j lcd_g2 e12 e bootsel3 b9 c iic2_sda c23 j lcd_g0 e13 e bootsel0 b10  va2 c24 g e14 d gio_p0 b11  g d1 c dtv_bclk e15 g b12  va3 d2 d dtv_psync e16 c jt0_tck b13  v d3 d dtv_vld e17 n testrstb b14  vio3 d4 d urt2_ctsb e18 m trstb
mc-10118b data sheet r19ds0008ej0700 7 (2/5) pin no. type pin name pin no. type pin name pin no. type pin name e19 j lcd_b5 h14 d gio_p1 k12  g e20 j lcd_b2 h15 g k13  g e21 j lcd_g5 h16 j debug_en k14  g e22 j lcd_r3 h17 e utest k15  g e23 j lcd_r2 h20 m ab0_csb0 k16 g e24 j lcd_r1 h21  vdd_ddr k17 ic f1  g h22  vdd_ddr k20 m ab0_a24 f2  g h23  vdd_ddr k21 m ab0_a23 f3  g h24  vdd_ddr k22 m ab0_a22 f4  g j1 d nts_data1 k23 m ab0_a21 f5 d gio_p7 j2 d nts_data2 k24 m ab0_a20 f6  g j3 d nts_data3 l1 d sd1_data1 f20 j lcd_r0 j4 d nts_data4 l2 d sd1_data2 f21 m ab0_csb3 j5 d nts_data6 l3 d sd1_data3 f22 m ab0_csb2 j8  g l4 d sd0_cmd f23  v j9  g l5 d sd0_data0 f24  v j10  g l8  g g1  vddq_ddr j11  g l9  g g2  vddq_ddr j12  g l10  g g3  vdd_ddr j13  g l11  g g4  vdd_ddr j14  g l12  g g5 d gio_p8 j15  g l13  g g20 m ab0_csb1 j16  g l14  g g21  g j17  g l15  g g22  g j20 m ab0_wait l16 g g23  g j21 m ab0_ben1 l17  g g24  g j22 m ab0_ben0 l20 m ab0_a19 h1 c nts_clk j23 m ab0_a26 l21  v h2 d nts_vs j24 m ab0_a25 l22  v h3 d nts_hs k1 c sd1_cki l23  vio18 h4 d nts_data0 k2 d sd1_cmd l24  vio18 h5 d nts_data5 k3 d sd1_cko m1  vio3 h8 d sp0_cs1 k4 d sd1_data0 m2  vio3 h9 d pm0_so k5 d nts_data7 m3  vio3 h10 d err_rst_reqb k8  g m4  vio3 h11  g k9  g m5 d sd0_data1 h12 q te1 k10 g m8 g h13 c a_resetb k11 g m9 g remark ic : internally-connected pins (leave open)
mc-10118b data sheet r19ds0008ej0700 8 (3/5) pin no. type pin name pin no. type pin name pin no. type pin name m10  g p8  g t4 d sd2_data2 m11  g p9  g t5 d gio_p10 m12  g p10  g t8  g m13  g p11  g t9  g m14  g p12  g t10  g m15  g p13  g t11  g m16  g p14  g t12  ic m17  g p15  g t13  ic m20 m ab0_a18 p16  g t14  g m21  g p17  g t15  g m22  g p20 m ab0_wrb t16 g m23  g p21 m ab0_rdb t17 g m24  g p22 p ab0_ad15 t20 p ab0_ad8 n1  g p23 p ab0_ad14 t21 p ab0_ad7 n2  g p24 p ab0_ad13 t22 p ab0_ad6 n3  g r1 c sd0_cki t23 p ab0_ad5 n4  g r2 d sd0_data2 t24 p ab0_ad4 n5  g r3 d sd0_data3 u1  v n8  g r4 d sd2_cmd u2  v n9  g r5 d gio_p9 u3  v n10  g r8  g u4  v n11  g r9  g u5  v n12  g r10  g u8  g n13  g r11  g u9  g n14  g r12  g u10  g n15 g r13  g u11  g n16 g r14  g u12  ic n17 g r15  g u13  ic n20 m ab0_a17 r16 g u14  ic n21  vdd_ddr r17 g u15 ic n22  vdd_ddr r20 p ab0_ad12 u16 ic n23  vdd_ddr r21 p ab0_ad11 u17 g n24  vdd_ddr r22 p ab0_ad10 u20 p ab0_ad3 p1  vdd_ddr r23 p ab0_ad9 u21  v p2  vdd_ddr r24 j ab0_clk u22  v p3  vddq_ddr t1 d sd0_cko u23  vio18 p4  vddq_ddr t2 d sd2_data0 u24  vio18 p5  vddq_ddr t3 d sd2_data1 v1 g remark ic : internally-connected pins (leave open)
mc-10118b data sheet r19ds0008ej0700 9 (4/5) pin no. type pin name pin no. type pin name pin no. type pin name v2  g y21 p ab0_ad0 ab12  ic v3  g y22 g ab0_adv ab13  ic v4  g y23 g usb_stp ab14  ic v5  g y24 g usb_clk ab15  g v20 p ab0_ad2 aa1 c sd2_cki ab16  ic v21  g aa2 d sd2_data3 ab17  ic v22  g aa3  ic ab18  vio18 v23  g aa4  ic ab19  g v24  g aa5  ic ab20  ic w1  vddq_ddr aa6  g ab21 g usb_data4 w2  vddq_ddr aa7  ic ab22 g usb_dir w3  vdd_ddr aa8  ic ab23 g usb_data3 w4  vdd_ddr aa9  ic ab24  g w5 ic aa10  g ac1  g w20 p ab0_ad1 aa11  v ac2  g w21  vdd_ddr aa12  ic ac3  ic w22  vdd_ddr aa13  ic ac4  ic w23  vdd_ddr aa14  ic ac5  v w24  vdd_ddr aa15  g ac6  g y1  vio3 aa16  ic ac7  vio18 y2  vio3 aa17  ic ac8  ic y3  vio3 aa18  vio18 ac9  ic y4  vio3 aa19  g ac10  g y5  ic aa20  ic ac11  vio18 y6  ic aa21 g usb_data7 ac12  ic y7  ic aa22 g usb_data6 ac13  ic y8  ic aa23 g usb_data5 ac14  ic y9  ic aa24 g usb_nxt ac15  g y10  ic ab1  g ac16  ic y11  v ab2 d sd2_cko ac17  ic y12  ic ab3  ic ac18  v y13  ic ab4  ic ac19  g y14  ic ab5  ic ac20  ic y15  ic ab6  g ac21 g usb_data1 y16  ic ab7  vio18 ac22 g usb_data2 y17  ic ab8  ic ac23  g y18  ic ab9  ic ac24  g y19  ic ab10  g ad1  g y20  ic ab11  vio18 ad2  g
mc-10118b data sheet r19ds0008ej0700 10 (5/5) pin no. type pin name ad3  g ad4  ic ad5  v ad6  g ad7  vio18 ad8  ic ad9  ic ad10  g ad11  vio18 ad12  ic ad13  ic ad14  ic ad15  g ad16  ic ad17  ic ad18  v ad19  g ad20 ic ad21 g usb_data0 ad22 g ad23 g ad24 g
mc-10118b data sheet r19ds0008ej0700 11 contents 1. pin funct ions .................................................................................................................. ................. 12 1.1 pin confi guration .............................................................................................................. .......... 12 1.2 pin func tions .................................................................................................................. ............ 13 1.3 i/o circuits ................................................................................................................... ................ 27 2. electrical spec ificat ions ...................................................................................................... ... 31 2.1 absolute maxi mum ra tings ....................................................................................................... 31 2.2 recommended operat ing condi tions ...................................................................................... 31 2.3 capacita nce ................................................................................................................................. 32 2.4 dc character istics ............................................................................................................. ......... 33 2.5 ac character istics ............................................................................................................. ......... 36 3. package dra wing................................................................................................................ ........... 60
mc-10118b data sheet r19ds0008ej0700 12 1. pin functions 1.1 pin configuration bootsel[3:0] det1 a _resetb c32k refclko pll2out err_rst_reqb osc12m_cki osc12m_cko a b0_clk a b0_ad[15:0] a b0_a[26:17] external bus interface a b0_ben[1:0] a b0_csb[3:0] pmx_clk a b0_wait a udio/voice interface pmx_sen a b0_wrb x 0 1 pmx_si a b0_rdb pmx_so a b0_adv spx_clk em1-d512 lcd_pxcl k spx_si spi interface spx_so lcd_r[5:0] x 0 2 sp0_cs[2:0] lcd_g[5:0] lcd interface sp1_cs[5:0] lcd_b[5:0] sp2_cs0 lcd_hsync lcd_vsync dtv_bclk lcd_enable terrestrial digital tv interface dtv_data dtv_psync usb_clk dtv_vld usb_data[7:0] nts_clk usb_dir usb interface itu-r bt.656 interface nts_vs usb_stp nts_hs usb_nxt usb_wakeup nts_data[7:0] usb_pw r_faultz sdx_cko iic_scl sd interface sdx_cmd iic_sda iic interface x 0 2 iic2_scl sdx_data[3:0] iic2_sda sdx_cki urtx_srin urtx_sout urt0_ctsb uart interface urt0 _ rtsb x 0 2 urt2_rtsb urt2_ctsb nand_ale nand_cle pwmx pwm interface x 0 1 nand_d[7:0] nand flash interface nand_oe gio_p[117:0] general-purpose i/o interface nand_we mw i_sk nand_rb[3:0] mwi_si microwire interface mw i_so nand_ce[3:0] mw i_cs debug_en utest jt0_tck tes trs tb jt0_trstb trs tb test pins jtag pins jt0_tms te1 jt0_tdi te2 jt0_tdo jt0_rtck 4 4 8 6 8 4 8 118 3 2 4 6 6 4 16 10 6 system interface osc12m_out cam sclk cam_yuv[7:0] cam_vs camera interface cam_hs cam_clki 8
mc-10118b data sheet r19ds0008ej0700 13 1.2 pin functions (1) bo ot select signals (vio18) pin name pin no. i/o function alternate pin function type handling when not used bootsel3 e12 input boot mode selection 3 ? e ? bootsel2 d12 input boot mode selection 2 ? e ? bootsel1 c12 input boot mode selection 1 ? e ? bootsel0 e13 input boot mode selection 0 ? e ? (2) system control signals (vio3 / vio18) pin name pin no. i/o function alternate pin function type handling when not used det1 b17 input power-on reset ? a ? a_resetb h13 input system reset ? c ?. c32k a9 input reference clock (32.768 khz) ? b . refclko a16 output reference clock pll2out osc12m_out d leave open. pll2out a16 output internal pll2 output refclko osc12m_out d leave open. osc12m_out a16 output internal osc output refclko pll2out d leave open. err_rst_reqb h10 output error reset request ? d leave open. osc12m_cki note a18 input osc xt1 ? z leave open. osc12m_cko note a17 output osc xt2 ? z leave open. note vio18
mc-10118b data sheet r19ds0008ej0700 14 (3) external bus interface signals (vio18) pin name pin no. i/o function alternate pin function type handling when not used ab0_clk r24 output clock gio_p11 nts_clk j leave open. ab0_ad[15:0] p22, p23, p24, r20, r21, r22, r23, t20, t21, t22, t23, t24, u20, v20, w20, y21 i/o data gio_p[27:12] p leave open. ab0_a[26:20] j23, j24, k20, k21, k22, k23, k24 output address gio_p[37:31] ab0_a[10:4] m leave open. ab0_a[19:17] l20, m20, n20 output address gio_p[30:28] nts_data[2:0] ab0_a[3:1] m leave open. ab0_a[10:4] j23, j24, k20, k21, k22, k23, k24 output address gio_p[37:31] ab0_a[26:20] m leave open ab0_a[3:1] l20, m20, n20 output address gio_p[30:28] nts_data[2:0] ab0_a[19:17] m leave open ab0_ben[1:0] j21, j22 output byte enable gio_p[47:46] m leave open. ab0_csb3 f21 output chip select gio_p45 nts_hs m leave open. ab0_csb2 f22 output chip select gio_p44 nts_vs m leave open. ab0_csb1 g20 output chip select gio_p43 nts_data7 m leave open. ab0_csb0 h20 output chip select gio_p42 nts_data6 m leave open. ab0_wait j20 input wait gio_p41 nts_data5 m leave open. ab0_wrb p20 output write strobe gio_p40 nts_data4 m leave open. ab0_rdb p21 output read strobe gio_p39 nts_data3 m leave open. ab0_adv y22 output address enable gio_p38 g leave open.
mc-10118b data sheet r19ds0008ej0700 15 (4) audio interface signals (vio3) pin name pin no. i/o function alternate pin function type handling when not used pm0_clk a8 i/o pcm0 clock (default input) ? c leave open. pm0_sen d9 i/o pcm0 frame synchronization (default input) ? d leave open. pm0_si e10 input pcm0 data gio_p87 d leave open. pm0_so h9 output pcm0 data ? d leave open. pm1_clk h1 i/o pcm1 clock (default input) gio_p72 nts_clk c leave open. pm1_sen h5 i/o pcm1 frame synchronization (default input) gio_p80 nts_data5 sp1_cs4 d leave open. pm1_si j5 input pcm1 data gio_p81 nts_data6 sp1_cs5 d leave open. pm1_so k5 output pcm1 data gio_p82 nts_data7 d leave open. (5) camera in terface sig nals (vio3) pin name pin no. i/o function alte rnate pin function type handling when not used cam_sclk e6 output camera clock gio_p5, nand_rb2 d leave open. cam_clki k1 input camera interface gio_p92, sd1_cki c leave open. cam_yuv7 l1 input camera interface sd1_data1 d leave open. cam_yuv6 k4 input camera interface sd1_data0 d leave open. cam_yuv5 k2 input camera interface sd1_cmd d leave open. cam_yuv4 j4 input camera interface nts_data4, sp1_cs3 gio_p79 d leave open. cam_yuv3 j3 input camera interface nts_data3, sp1_cs2 gio_p78 d leave open. cam_yuv2 j2 input camera interface nts_data2, sp1_cs1 gio_p77 d leave open. cam_yuv1 j1 input camera interface nts_data1, sp1_cs0 gio_p76 d leave open cam_yuv0 h4 input camera interface nts_data0, sp1_so gio_p75 d leave open cam_hs l3 input camera interface sd1_data3 d leave open cam_vs l2 input camera interface sd1_data2 d leave open
mc-10118b data sheet r19ds0008ej0700 16 (6) spi interface signals (vio3) pin name pin no. i/o function alternate pin function type handling when not used sp0_clk b8 i/o spi0 clock output mwi_sk d leave open. sp0_si c8 input spi0 data mwi_si d leave open. sp0_so d8 output spi0 data mwi_so d leave open. sp0_cs0 e9 i/o spi0 chip select mwi_cs d leave open. sp0_cs[2:1] e8, h8 output spi0 chip select gio_p[49:48] d leave open. sp1_clk h2 i/o spi1 clock input gio_p73 nts_vs d leave open. sp1_si h3 input spi1 data gio_p74 nts_hs d leave open. sp1_so h4 output spi1 data gio_p75 nts_data0 cam_yuv0 d leave open. sp1_cs5 j5 output spi1 chip select gio_p81 nts_data6 pm1_si d leave open. sp1_cs4 h5 output spi1 chip select gio_p80 nts_data5 pm1_sen d leave open. sp1_cs[3:1] j4, j3, j2 output spi1 chip select gio_p[79:77] nts_data[4:2] cam_yuv[4:2] d leave open. sp1_cs0 j1 i/o spi1 chip select gio_p76 nts_data1 cam_yuv1 d leave open. sp2_clk d1 i/o spi2 clock input dtv_bclk c leave open. sp2_si c2 input spi2 data dtv_data d leave open. sp2_so d2 output spi2 data dtv_psync d leave open. sp2_cs0 d3 i/o spi2 chip select dtv_vld d leave open. (7) t errestrial digital tv interface signals (vio3) pin name pin no. i/o function alternate pin function type handling when not used dtv_bclk d1 input clock sp2_clk c leave open. dtv_data c2 input yuv data sp2_si d leave open. dtv_psync d2 input vertical sy nchronization sp2_so d leave open. dtv_vld d3 input horizontal sy nchronization sp2_cs0 d leave open.
mc-10118b data sheet r19ds0008ej0700 17 (8) lcd interface signals (vio18) pin name pin no. i/o function alternate pin function type handling when not used lcd_pxclk d24 output pixel clock gio_p50 j leave open. lcd_r[5:0] d22, d23, e22, e23, e24, f20 output red data gio_p[56:51] j leave open. lcd_g[5:0] e21, d21, c21, c22, b22, c23 output green data gio_p[62:57] j leave open. lcd_b[5:0] e19, d19, c19, e20, d20, c20 output blue data gio_p[68:63] j leave open. lcd_hsync b18 output horizontal synchronization gio_p69 j leave open. lcd_vsync c18 output vertical synchronization gio_p70 j leave open. lcd_enable d18 output data enable gio_p71 j leave open. (9) usb in terface sig nals (vio18 / vio3) pin name pin no. i/o function alternate pin function type handling when not used usb_clk y24 input clock gio_p96 g leave open. usb_data[7:0] aa21, aa22, aa23, ab21, ab23, ac22, ac21, ad21 i/o usb data gio_p[104:97] g leave open. usb_dir ab22 input usb dir input gio_p105 g leave open. usb_stp y23 output usb stop output gio_p106 g leave open. usb_nxt aa24 input usb nxt input gio_p107 g leave open. usb_wakeup note h14 output suspend wakeup gio_p1 usb_pwr_fault d leave open. usb_pwr_fault note h14 input power fault gio_p1 usb_wakeup d leave open. note vio3
mc-10118b data sheet r19ds0008ej0700 18 (10) itu-r bt.656 interface signals (vio3 / vio18) pin name pin no. i/o function alte rnate pin function type handling when not used h1 gio_p72, pm1_clk c leave open. nts_clk r24 note input clock ab0_clk, gio_p11 j leave open h2 gio_p73, sp1_clk d leave open. nts_vs f22 note output vertical synchronization ab0_csb2, gio_p44 m leave open. h3 gio_p74, sp1_si d leave open. nts_hs f21 note output horizontal synchronization ab0_csb3, gio_p45 m leave open. k5 gio_p82, pm1_so d leave open. nts_data7 g20 note output ntsc data ab0_csb1, gio_p43 m leave open j5 gio_p81, sp1_cs5 pm1_si d leave open. nts_data6 h20 note output ntsc data ab0_csb0, gio_p42 m leave ope h5 gio_p80, sp1_cs4 pm1_sen d leave open. nts_data5 j20 note output ntsc data ab0_wait, gio_p41 m leave open. j4 gio_p79, sp1_cs3 cam_yuv4 d leave open. nts_data4 p20 note output ntsc data ab0_wrb, gio_p40 m leave open. j3 gio_p78, sp1_cs2 cam_yuv3 d leave open. nts_data3 p21 note output ntsc data ab0_rdb, gio_p39 m leave open j2 gio_p77, sp1_cs1 cam_yuv2 d leave open. nts_data2 l20 note output ntsc data ab0_a3, ab0_a19, gio_p30 m leave open j1 gio_p76, sp1_cs0 cam_yuv1 d leave open. nts_data1 m20 note output ntsc data ab0_a2, ab0_a18, gio_p29 m leave ope h4 gio_p75, spi_so cam_yuv0 d leave open. nts_data0 n20 note output ntsc data ab0_a1, ab0_a17, gio_p28 m leave open. note vio18
mc-10118b data sheet r19ds0008ej0700 19 (11) iic interface signals (vio3) pin name pin no. i/o function alte rnate pin function type handling when not used iic_scl d10 output serial clock input gio_p83 c leave open. iic_sda c10 i/o serial data input gio_p84 c leave open. iic2_scl c9 output serial clock input nand_we c leave open. iic2_sda b9 i/o serial data input nand_rb0 c leave open. (12) ua rt interface signals (vio3) pin name pin no. i/o function alternate pin function type handling when not used urt0_srin a5 input serial data ? d leave open. urt0_sout b5 output serial data ? d leave open. urt0_ctsb d5 input data transmission/reception ready in destination device gio_p85 urt1_srin d leave open. urt0_rtsb c5 output data transmission/reception ready gio_p86 urt1_sout d leave open. urt1_srin d5 input serial data gio_p85 urt0_ctsb d leave open. urt1_sout c5 output serial data gio_p86 urt0_rtsb d leave open. urt2_srin c3 input serial data gio_p108 nand_ale d leave open. urt2_sout b3 output serial data gio_p109 nand_cle d leave open. urt2_ctsb d4 input data transmission/reception ready in destination device gio_p110 nand_d0 d leave open. urt2_rtsb c4 output data transmission/reception ready gio_p111 nand_d1 d leave open.
mc-10118b data sheet r19ds0008ej0700 20 (13) memo ry card interface signals (vio3) pin name pin no. i/o function alternate pin function type handling when not used sd0_cko t1 output clock  d leave open. sd0_cmd l4 i/o command response  d leave open. sd0_data[3:1] r3, r2, m5 i/o data gio_p[90:88] d leave open. sd0_data0 l5 i/o data  d leave open. sd0_cki r1 input loop back gio_p91 c leave open. sd1_cko k3 output clock ? d leave open. sd1_cmd k2 i/o command response cam_yuv5 d leave open. sd1_data3 l3 i/o data cam_hs d leave open. sd1_data2 l2 i/o data cam_vs d leave open. sd1_data1 l1 i/o data cam_yuv7 d leave open. sd1_data0 k4 i/o data cam_yuv6 d leave open. sd1_cki k1 input loop back gio_p92 cam_clki c leave open. sd2_cko ab2 output clock gio_p112 nand_d2 d leave open. sd2_cmd r4 i/o command response gio_p113 nand_d3 d leave open. sd2_data[3:0] aa2, t4, t3, t2 i/o data gio_p[117:114] nand_d[7:4] d leave open. sd2_cki aa1 input loop back gpio_p93 nand_oe c leave open. (14) pw m interface signals (vio3) pin name pin no. i/o function alternate pin function type handling when not used pwm0 a4 output pwm output gio_p94 d leave open. pwm1 b4 output pwm output gio_p95 d leave open.
mc-10118b data sheet r19ds0008ej0700 21 (15) general-purpose i/o interface signals (vio18 / vio3) (1/3) pin name pin no. i/o function alternate pin function type handling when not used gio_p[117:114] aa2, t4, t3, t2 i/o general-purpose io sd2_data[3:0] nand_d[7:4] d leave open. gio_p113 r4 i/o general-purpose io sd2_cmd nand_d3 d leave open. gio_p112 ab2 i/o general -purpose io sd2_cko nand_d2 d leave open. gio_p111 c4 i/o general-purpose io urt2_rtsb nand_d1 d leave open. gio_p110 d4 i/o general-purpose io urt2_ctsb nand_d0 d leave open. gio_p109 b3 i/o general-purpose io urt2_sout nand_cle d leave open. gio_p108 c3 i/o general-purpose io urt2_srin nand_ale d leave open. gio_p107 note aa24 i/o general-purpose io usb_nxt g leave open. gio_p106 note y23 i/o general-purpose io usb_stp g leave open. gio_p105 note ab22 i/o general-purpose io usb_dir g leave open. gio_p[104:97] note aa21, aa22, aa23, ab21, ab23, ac22, ac21, ad21 i/o general-purpose io usb_data[7:0] g leave open. gio_p96 note y24 i/o general-purpose io usb_clk g leave open. gio_p[95:94] b4, a4 i/o general-purpose io pwm[1:0] d leave open. gio_p93 aa1 i/o general-purpose io sd2_cki nand_oe c leave open. gio_p92 k1 i/o general-purpose io sd1_cki cam_clki c leave open. gio_p91 r1 i/o general-purpose io sd0_cki c leave open. gio_p[90:88] r3, r2, m5 i/o general-purpose io sd0_data[3:1] d leave open. gio_p87 e10 i/o general-purpose io pm0_si d leave open. gio_p86 c5 i/o general-purpose io urt0_rtsb urt1_sout d leave open. gio_p85 d5 i/o general-purpose io urt0_ctsb urt1_srin d leave open. gio_p84 c10 i/o general-purpose io iic_sda c leave open. gio_p83 d10 i/o general-purpose io iic_scl c leave open.
mc-10118b data sheet r19ds0008ej0700 22 (2/3) pin name pin no. i/o function alternate pin function type handling when not used gio_p82 k5 i/o general-purpose io nts_data7 pm1_so d leave open. gio_p81 j5 i/o general-purpose io nts_data6 sp1_cs5 pm1_si d leave open. gio_p80 h5 i/o general-purpose io nts_data5 sp1_cs4 pm1_sen d leave open. gio_p[79:76] j4, j3, j2, j1 i/o general-purpose io nts_data[4:1] sp1_cs[3:0] cam_yuv[4:1] d leave open. gio_p75 h4 i/o general-purpose io nts_data0 sp1_so cam_yuv0 d leave open. gio_p74 h3 i/o general-purpose io nts_hs sp1_si d leave open. gio_p73 h2 i/o general-purpose io nts_vs sp1_clk d leave open. gio_p72 h1 i/o general-purpose io nts_clk pm1_clk c leave open. gio_p71 note d18 i/o general-purpose io lcd_enable j leave open. gio_p70 note c18 i/o general-purpose io lcd_vsync j leave open. gio_p69 note b18 i/o general-purpose io lcd_hsync j leave open. gio_p[68:63] note e19, d19, c19, e20, d20, c20 i/o general-purpose io lcd_b[5:0] j leave open. gio_p[62:57] note e21, d21, c21, c22, b22, c23 i/o general-purpose io lcd_g[5:0] j leave open. gio_p[56:51] note d22, d23, e22, e23, e24, f20 i/o general-purpose io lcd_r[5:0] j leave open. gio_p50 note d24 i/o general-purpose io lcd_pxclk j leave open. gio_p[49:48] note e8, h8 i/o general-purpose io sp0_cs[2:1] d leave open. gio_p[47:46] note j21,j22 i/o general-purpose io ab0_ben[1:0] m leave open. gio_p45 note f21 i/o general-purpose io ab0_csb3 nts_hs m leave open. gio_p44 note f22 i/o general-purpose io ab0_csb2 nts_vs m leave open. gio_p43 note g20 i/o general- purpose io ab0_csb1 nts_data7 m leave open. gio_p42 note h20 i/o general-purpose io ab0_csb0 nts_data6 m leave open.
mc-10118b data sheet r19ds0008ej0700 23 (3/3) pin name pin no. i/o function alternate pin function type handling when not used gio_p41 note j20 i/o general-purpose io ab0_wait nts_data5 m leave open. gio_p40 note p20 i/o general-purpose io ab0_wrb nts_data4 m leave open. gio_p39 note p21 i/o general-purpose io ab0_rdb nts_data3 m leave open. gio_p38 note y22 i/o general-purpose io ab0_adv g leave open. gio_p[37:31] note j23, j24, k20, k21, k22, k23, k24 i/o general-purpose io ab0_a[26:20] ab0_a[10:4] m leave open. gio_p[30:28] note l20, m20, n20 i/o general-purpose io ab0_a[19:17] nts_data[2:0] ab0_a[3:1] m leave open. gio_p[27:12] note p22, p23, p24, r20, r21, r22, r23, t20, t21, t22, t23, t24, u20, v20, w20, y21 i/o general-purpose io ab0_ad[15:0] p leave open. gio_p11 note r24 i/o general-purpose io ab0_clk nts_clk j leave open. gio_p[10:7] t5, r5, g5, f5 i/o general-purpose io nand_ce[3:0] d leave open. gio_p6 e5 i/o general-purpose io nand_rb3 d leave open. gio_p5 e6 i/o general-purpose io nand_rb2 cam_sclk d leave open. gio_p4 e7 i/o general-purpose io nand_rb1 d leave open. gio_p[3:2] d13, c13 i/o general-purpose io ? d leave open. gio_p1 h14 i/o general-purpose io usb_wakeup usb_pwr_faul t d leave open. gio_p0 e14 i/o general-purpose io ? d leave open. note vio18
mc-10118b data sheet r19ds0008ej0700 24 (16) microwire interface signals (vio3) pin name pin no. i/o function alternate pin function type handling when not used mwi_sk b8 output clock sp0_clk d leave open. mwi_si c8 input data sp0_si d leave open. mwi_so d8 output data sp0_so d leave open. mwi_cs e9 output chip select sp0_cs0 d leave open. (17) na nd flash interface signals (vio3) pin name pin no. i/o function alternate pin function type handling when not used nand_ale c3 output address latch enable urt2_srin gio_p108 d leave open. nand_cle b3 output command latch enable urt2_sout gio_p109 d leave open. nand_d[7:4] aa2, t4 t3, t2 i/o data sd2_data[3:0] gio_p[117:114] d leave open. nand_d3 r4 i/o data sd2_cmd gio_p113 d leave open. nand_d2 ab2 i/o data sd2_cko gio_p112 d leave open. nand_d1 c4 i/o data urt2_rtsb gio_p111 d leave open. nand_d0 d4 i/o data urt2_ctsb gio_p110 d leave open. nand_oe aa1 output output enable sd2_cki gio_p93 c leave open. nand_we c9 output write enable iic2_scl c leave open. nand_rb0 b9 input ready busy iic2_sda c leave open. nand_rb3 e5 input ready busy gio_p6 d leave open. nand_rb2 e6 input ready busy gio_p5 cam_sclk d leave open. nand_rb1 e7 input ready busy gio_p4 d leave open. nand_ce[3:0] t5, r5, g5, f5 output chip enable gio_p[10:7] d leave open.
mc-10118b data sheet r19ds0008ej0700 25 (18) jtag signals (vio18 / vio3) pin name pin no. i/o function alternate pin function type handling when not used debug_en note h16 input jtag ? j leave open. jt0_tck e16 input jtag ? c leave open. jt0_trstb d17 input jtag ? c leave open. jt0_tms b16 input jtag ? d leave open. jt0_tdi c16 input jtag ? d leave open. jt0_tdo d16 output jtag ? d leave open. jt0_rtck c17 output jtag ? d leave open. note vio18 (19) t est signals (vio18) pin name pin no. i/o function alternate pin function type handling when not used utest h17 input test pin (usually fixed to 0) ? e ?l? level hold. testrstb e17 input asynchronous reset for testing ? n leave open. trstb e18 input test pin ? m leave open. te1 h12 input test pin ? q leave open. te2 e11 input test pin ? r leave open. (20) pow er supply pin name pin no. i/o function type handling when not used v a7, a13, a20, b7, b13, b20, e1, e2, f23, f24, l21, l22, u1, u2, u3, u4, u5, u21, u22, y11, aa11, ac5, ac18, ad5, ad18 ? core power supply (1.2 v) ? ? vio18 a21, b21, e3, e4, l23, l24, u23, u24, aa18, ab7, ab11, ab18, ac7, ac11, ad7, ad11 ? io power supply (1.8 v system) ? ? vio3 a14, b14, c7, c14, d7, d14, m1, m2, m3, m4, y1, y2, y3, y4 ? io power supply (3 v system) ? ? va1 c11, d11 ? pll power supply (1.2v) ? ? va2 a10, b10 ? pll power supply (1.2v) ? ? va3 a12, b12 ? pll power supply (1.2v) ? ? vddq_ddr g1, g2, p3, p4, p5, w1, w2 ? ddr power supply (1.8v) ? ? vdd_ddr g3, g4, h21, h22, h23, h24, n21, n22, n23, n24, p1, p2, w3, w4, w21 ,w22, w23, w24 ? ddr power supply (1.8v) ? ?
mc-10118b data sheet r19ds0008ej0700 26 (21) gnd pin name pin no. function g a1, a2, a3, a6, a11, a15, a19, a22, a23, a24, b1, b2, b6, b11, b15, b19, b23, b24, c1, c6, c15, c24, d6, d15, e15, f1, f2, f3, f4, f6, g21, g22, g23, g24, h11, h15, j8, j9, j10, j11, j12, j13, j14, j15, j16, j17,k8, k9, k10, k11, k12, k13, k14, k15, k16, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, m8, m9, m10, m11, m12, m13, m14, m15, m16, m17, m21, m22, m23, m24, n1, n2, n3, n4, n5, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, p8, p9, p10, p11, p12, p13, p14, p15, p16, p17, r8, r9, r10, r11, r12, r13, r14, r15, r16, r17, t8, t9, t10, t11, t14, t15, t16, t17, u8, u9, u10, u11, u17, v1, v2, v3, v4, v5, v21, v22, v23, v24, aa6, aa10, aa15, aa19, ab1, ab6, ab10, ab15, ab19, ab24, ac1, ac2, ac6, ac10, ac15, ac19, ac23, ac24, ad1, ad2, ad3, ad6, ad10, ad15, ad19, ad22, ad23, ad24 gnd (22) other pin name pin no. i/o function type handling when not used ic k17, t12, t13, u12, u13, u14, u15, u16, w5, y5, y6, y7, y8, y9, y10, y12, y13, y14, y15, y16, y17, y18, y19, y20, aa3, aa4, aa5, aa7, aa8, aa9, aa12, aa13, aa14, aa16, aa17, aa20, ab3, ab4, ab5, ab8, ab9, ab12, ab13, ab14, ab16, ab17, ab20, ac3, ac4, ac8, ac9, ac12, ac13, ac14, ac16, ac17, ac20, ad4, ad8, ad9, ad12, ad13, ad14, ad17, ad16, ad20 ? internally-connected pins ? ?
mc-10118b data sheet r19ds0008ej0700 27 1.3 i/o circuits (1/4) type a description io-standby go-around signal a y input buffer schmitt (vio3) w / io-standby control other io buffers are fixed on the time of power off mode in pow off state of appendix d by inputting the low level to this buffer. remark in the power-off mode, pins remain in a hi-z state (input) and the signals are passed through this buffer. types b, e description 50 k ? y0 oen a y1 c0 c1 upc poenb normal bidirectional buffer schmitt (type b = vio3, type e = vio18) w / iolh control normal / pull-up 50 k ? / pull-down 50 k ? ? during power-off: pins remain in a hi-z state ? resistance = 50 k ? (typ.) type c description 50 k ? y0 oen a y1 c0 c1 upc poenb normal bidirectional buffer schmitt (vio3) w / iolh control normal / pull-up 50 k ? / pull-down 50 k ? ? during power-off: pins remain in a hi-z state (masked by 0 internally) ? resistance = 50 k ? (typ.)
mc-10118b data sheet r19ds0008ej0700 28 (2/4) type d description 50 k ? y0 oen a y1 c0 c1 upc poenb normal ctl bidirectional buffer and (vio3) w / iolh control normal / pull-up 50 k ? / pull-down 50 k ? ? during power-off: pins remain in a hi-z state (masked by 0 internally) ? resistance = 50 k ? (typ.) types g description 50 k ? y0 oen a y1 c0 c1 upc poenb normal ctl bidirectional buffer and (vio18) w / iolh control normal / pull-up 50 k ? pull-down 50 k ? ? during power-off: type g: pins are pulled down (masked by 0 internally) ? resistance = 50 k ? (typ.) type j description 50 k ? y0 oen a y1 c0 c1 upc poenb normal ctl bidirectional buffer a nd, schmitt (vio18) w / iolh control normal / pull-up 50 k ? / pull-down 50 k ? ? during power-off: pins are pulled down (masked by 0 internally) ? resistance = 50 k ? (typ.)
mc-10118b data sheet r19ds0008ej0700 29 (3/4) types m, n description 50 k ? y0 oen a y1 c0 c1 upc poenb low noise bidirectional buffer schm itt / lownoise (vio18) w / iolh control normal / pull-up 50 k ? / pull-down 50 k ? ? during power-off: type m: pins are pulled down (masked by 0 internally) type n: pins are pulled up (masked by 0 internally) ? resistance = 50 k ? (typ.) type p description 6.5 k ? ? y0 oen a y1 c0 c1 normal busholder bidirectional buffer (vio18) w / iolh control bus holder ? during power-off: pins output a low level (masked by 0 internally) ? resistance = 6.5 k ? (typ.) types q, r description go-around signal 50 k ? a test buffer (vio18) types q and r are buffers used exclusively for testing. leave open when used in the actual device. (always pull down the pins (typ. 50 k ? )
mc-10118b data sheet r19ds0008ej0700 30 (4/4) type z description oscillator xt2 xt1
mc-10118b data sheet r19ds0008ej0700 31 2. electrical specifications 2.1 absolute maximum ratings parameter symbol conditions rating unit v 1.2 v system ?0.5 to +1.8 v v io18 1.8 v system (i/o) ?0.5 to +2.5 v v io3 3 v system (i/o) ?0.5 to +4.6 v power supply voltage v dd_ddr v ddq_ddr power supply for memories ?0.5 to +2.3 v v i_18 1.8 v system (i/o) ?0.5 to v io18 + 0.5 v input voltage v i_33 3 v system (i/o) ?0.5 to v io3 + 0.5 v v o_18 1.8 v system (i/o) ?0.5 to v io18 + 0.5 v output voltage v o_33 3 v system (i/o) ?0.5 to v io3 + 0.5 v storage temperature t stg  ?40 to +125 ? c caution product quality may suffer if the absolute m aximum rating is exceeded ev en momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. note instantaneous input of a voltage in the range of ? 0.8 to v dd12 + 0.8 v is allowed as long as capacitive coupling is implemented. 2.2 recommended operating conditions parameter symbol conditions min. typ. max. unit 1.2 v system, during normal operation 1.1 1.2 1.3 v v memory retention voltage note 1 0.64   v v _pll 1.2 v system (pll power supply, pin: va) 1.1 1.2 1.3 v v io18 1.8 v system (i/o power supply) 1.7 1.8 1.9 v v io3 3 v system (i/o power supply) 2.7  3.6 v power supply voltage v dd_ddr v ddq_ddr power supply for memories 1.7 1.8 1.9 v oscillation start voltage note 2 v osc_s  1.7   v oscillation start voltage note 3 v osc_h  1.7   v operating ambient temperature t a  ?20  +70 ? c notes 1. this is the voltage that guarantees retention of dat a in the internal sram when the voltage drops during normal operation. 2. this is the voltage at which oscillation always starts after power-on. 3. this is the voltage that guarantees oscillati on when the voltage drops during normal operation.
mc-10118b data sheet r19ds0008ej0700 32 2.3 capacitance (t a = +25 ? c, f = 1 mhz, unmeasured pins returned to 0 v) parameter symbol conditions min. typ. max. unit 1.8 v 3  5 pf input capacitance c i 2.8 v 2  4 pf 1.8 v 3  5 pf output capacitance c o 2.8 v 2  4 pf 1.8 v 3  5 pf i/o capacitance c io 2.8 v 2  4 pf
mc-10118b data sheet r19ds0008ej0700 33 2.4 dc characteristics 2.4.1 vio18 (unless it' s designated in particular by the item after this, it'll be the standard under 2.2 recommendation operating condition. ) parameter symbol conditions min. typ. max. unit output voltage, high v oh no dc load note 1 v io18 ? 0.1   v output voltage, low v ol no dc load note 1   0.1 v input voltage, high v ih i/o pins and monitor pins 0.65 ? v io18  v io18 + 0.5 v input voltage, low v il i/o pins and monitor pins ?0.5  0.35 ? v io18 v i out_h1 2 ma setting note 3 1.7   ma i out_h2 4 ma setting note 3 3.7   ma i out_h3 6 ma setting note 3 5.7   ma i out_h4 8 ma setting note 3 7.7   ma output current, high v oh = v io18 ? 0.4 v note 2 i out_h5 12 ma setting note 3 11.0   ma i out_l1 2 ma setting note 3 1.7   ma i out_l2 4 ma setting note 3 3.7   ma i out_l3 6 ma setting note 3 5.7   ma i out_l4 8 ma setting note 3 7.7   ma output current, low v ol = 0.4 v note 2 i out_l5 12 ma setting note 3 11.0   ma hysteresis voltage v h schmitt input 0.20 ? v io18  0.63 ? v io18 v negative trigger voltage v n schmitt input 0.53 ? v io18 ? 0.66  0.35 ? v io18 v positive trigger voltage v p schmitt input 0.68 ? v io18  0.83 ? v io18 v input leakage current, high i l_h v i = v io18   1 ? a input leakage current, low i l_l v i = gnd   1 ? a pull-up resistance r pu  40  65 k ? pull-down resistance r pd  40  65 k ? bus-holder hold resistance r bh bus-holder series resistance 5  11 k ? pull-up pin current i pu    50 ? a pull-down pin current i pd    50 ? a notes 1. the parameters v oh and v ol here are the values guaranteed when there is no load when applying the dc current. 2. the parameters v oh and v ol here define the output current. 3. this is the value set to the i/o buffe r output current drive switch register.
mc-10118b data sheet r19ds0008ej0700 34 2.4.2 vio3 parameter symbol conditions min. typ. max. unit output voltage, high v oh no dc load note 1 v io3 ? 0.1   v output voltage, low v ol no dc load note 1   0.1 v input voltage, high v ih i/o pins and monitor pins 2.0  v io3 + 0.5 v input voltage, low v il i/o pins and monitor pins ?0.5  0.8 v i out_h1 2 ma setting note 3 1.7   ma i out_h2 4 ma setting note 3 3.7   ma i out_h3 6 ma setting note 3 5.7   ma output current, high v oh = v io3 ? 0.4 v note 2 i out_h4 8 ma setting note 3 7.7   ma i out_l1 2 ma setting note 3 1.7   ma i out_l2 4 ma setting note 3 3.7   ma i out_l3 6 ma setting note 3 5.7   ma output current, low v ol = 0.4 v note 2 i out_l4 8 ma setting note 3 7.7   ma hysteresis voltage v h schmitt input 0.11 ? v io3  0.41 ? v io3 v negative trigger voltage v n schmitt input 0.17 ? v io3  0.38 ? v io3 v positive trigger voltage v p schmitt input 0.54 ? v io3  0.65 ? v io3 v input leakage current, high i l_h v i = v io3   1 ? a input leakage current, low i l_l v i = gnd   1 ? a pull-up resistance r pu 50 k ? resistor 40  65 k ? pull-down resistance r pd 50 k ? resistor 40  65 k ? pull-up pin current i pu 50 k ? resistor   90 ? a pull-down pin current i pd 50 k ? resistor   90 ? a notes 1. the parameters v oh and v ol here are the values guaranteed when there is no load when applying the dc current. 2. v ol = 0.4 v, v oh = v io3 ? 0.4 v. the parameters v oh and v ol here define the output current. 3. this is the value set to the output current drive switch register. 2.4.3 standby state current (logic) (t a = 25 ?c) parameter symbol conditions min. typ. max. unit logic power supply l0 + l2 on, f = 0 hz, v = 0.75 v  130 400 ? a logic power supply l0 on, f = 0 hz, v = 0.75 v  100 300 ? a i dd_l0 logic power supply l0 on, f = 0 hz, v = 1.2 v  340  ? a i dd_io18 io power supply f = 0 hz, v io18 = 1.8 v   10 ? a standby current i dd_io3 io power supply f = 0 hz, v io3 = 2.85 v   10 ? a
mc-10118b data sheet r19ds0008ej0700 35 2.4.4 standby state current (mobile ddr sdram) parameter symbol conditions min. typ. max. unit standby current (deep power-down mode) ddr idd7 cke ?0.2v   10 a 2.4.5 self refresh current parameter symbol conditions min. typ. max. unit pasr = ?000? (full)   500 a pasr = ?001? (2bk)   400 a pasr = ?010? (1bk) ddr idd6 -25 ? c ?ddr_t j ?+85 ? c cke ?0.2v   300 a
mc-10118b data sheet r19ds0008ej0700 36 2.5 ac characteristics 2.5.1 ac test i/o measurement points figure 2-1. a c test i/o measurement points load condition output pin dut c l = 15 pf input pin input measurement points v io18 v io3 0.7 ? v io 0.7 ? v io 0.3 ? v io 0.3 ? v io v io18 v io3 output pin output measurement points 0.5 v dd 0.5 v dd input pin (schmitt) input measurement points v io18 v io3 0.8 ? v io 0.8 ? v io 0.1 ? v io 0.1 ? v io remark excluding the osc pin. unless specified otherwise, the load of c l is assumed to be 15 pf. unless it's designated in particular by the item after this, it'll be the standard under 2.2 recommendation operating condition
mc-10118b data sheet r19ds0008ej0700 37 2.5.2 system control (1) clock (input timing requirements) parameter symbol conditions min. typ. max. unit c32k frequency f clkc32k   32.768  khz c32k rise/fall time t rfc32k 10 to 90%   1 ? s 32 khz input clock duty ratio i dutyc32k  40 50 60 % 32 khz input clock jitter i jitterc32k  ?20  20 ns osc oscillation frequency range f c(osc) internal oscillator (osc12m_cki or osc12m_cko) (with crystal resonator dsx530ga; made by daishinku)   13 mhz osc clock stabilization time t stab12 ci = co = 15 pf the oscillating frequency : 12mhz (with crystal resonator dsx530ga; made by daishinku)  0.5 1 ms figure 2-2. clock timing input clock c32k t rfc32k t rfc32k t wc32k(h) t wc32k(l) 1/f clkc32k figure 2-3. recommended oscillator osc12m_cki osc12m_cko cautions 1. keep the wiring length between the o scillator and the osc12m_cki and osc12m_cko pins as short as possible. 2. do not cross the wiring with the other signal lines in the area enclosed by the broken lines. 3. thoroughly evaluate matching of the resonator.
mc-10118b data sheet r19ds0008ej0700 38 (2) reset (a_resetb) parameter symbol conditions min. typ. max. unit a_resetb low-level width t a_resetb  6   ms remark in the case of a hardware reset. figure 2-4. reset timing a_resetb t rstib , t a_resetb (3) power supply start-up timing (without power supply -> normal) det1 a_resetb (inside pll) c32k min:200us core power supply (v) pll power supply (va1/2/3) io power supply (vio18) time when a vio3 power supply becomes stable. (1) (2) (3) (4) min:200us (5) io power supply (vio3) (6) time when a vio18 power supply becomes stable. min:0us time when v,va1,va2,va3 power supply becomes stable. figure 2-5. power supply start-up timing remarks ?stable? means that each power s upply becomes the specification minimum voltage. the timing figure which starts from the ?without power supply?. (1) io power supply (vio18) is supplied, and st ands by until a power supply becomes stable. (2) io power supply (vio3) is supplied, and st ands by until a power supply becomes stable. (3) corepower supply (v) and pll power supply (va1/2/3) are supplied, and stands by until a power supply becomes stable. (4) rtc clock 32.768khz (c32k) is input. (5) det1 is signal is started. (6) a_resetb signal rising (reset rel ease), and pll begins to oscillate.
mc-10118b data sheet r19ds0008ej0700 39 (4) power supply start-up timing (deepsleep<- -> normal) io power supply (vio18,vio3) det1 a_resetb (inside pll) c32k core power supply (v) min:2ms gio_p0 (1) (2) (3) (4) normal deepsleep pll power supply (va1/2/3) ?off?setting min:0ms normal ?0.75v? setting figure 2-6. deepsleep normal timing (1) em1-d512 sends the command to power management ic by spi interface. the cont ents of the command are as follows. core power supply (v) voltage is changed to 0. 75 from 1.2v. pll power supply (va1/2/3) is stopped. (2) power management ic changes the core power supply (v) to 0.75v from 1.2v in at least 2 ms later and stops pll power supply (va1/2/3). em1-d512 does the preparations to transfer to t he deepsleep state between (1) and (2). (3) core power supply (v) voltage is changed to 1.2v fr om 0.75v. vpll power supply (va1/2/3) is supplied. (4) gio_p0 signal rising and inside pll begins to oscillate. em1-d512 is transit of stat e from deepsleep to normal after inside pll stable.
mc-10118b data sheet r19ds0008ej0700 40 (5) power supply start-up timing (poweroff<- -> normal) io power supply (vio18,vio3) det1 a_resetb (inside pll) c32k core power supply(v) pll power supply(va1/2/3) gio_p0 (1) (2)(3) (5) (4) normal min:0us min:0us min:0us min:0us min:200us min:200us poweroff normal figure 2-7. poweroff normal timing (1) a_resetb signal and det1 signal are falling, and rtc cl ock (c32k) is stop. next core power supply and pll power supply are stopped at the same time. (2) core power supply (v) and pll power supply (va1/2/3) are supplied same time, and stand by until a power supplies become stable. (3) rtc clock 32.768khz (c32k) is input. gio_p0 signal rising. it's to make em1-d512 recognizes that it's different from "without power supply". (4) det1 is signal is started. (5) a_resetb signal rising (reset releas e), and inside pll begins to oscillate.
mc-10118b data sheet r19ds0008ej0700 41 2.5.3 asynchronous bus (ab0) interface parameter symbol conditions min. typ. max. unit asynchronous single read access time t 201 note (1 + t0 + t1 + t2) ? tf ? 3  (2 + t0 + t1 + t2) ? tf + 3 ns csz rise to advz fall t 202 note tf ? 3  2tf + 3 ns advz active width t 203 ab0_advz = low tf ? 3  tf + 3 ns lower add for admux hold time t 204  t0 ? tf ? 3  t0 ? tf + 3 ns delay time from advz rise to read signal output t 205 falling edge of ab0_rdz t0 ? tf ? 3  t0 ? tf + 3 ns read signal active width t 206 ab0_rdz = low t1 ? tf ? 3  t1 ? tf + 3 ns delay time from rdz rise to csz fall output t 207 rising edge of ab0_rdz t2 ? tf ? 3  t2 ? tf + 3 ns cs assert interval time t 208  csint ? tf ? 3   ns asynchronous _rdata setup time t 209 rising edge of ab0_rdz 15   ns asynchronous _rdata hold time t 210 rising edge of ab0_rdz 0   ns delay time from address determination to rdz fall t 211 falling edge of ab0_rdz note (1 + t0) ? tf ? 8   ns delay time from csz fall to rdz rise output t 212 falling edge of ab0_rdz note (1 + t0) ? tf ? 3   ns asynchronous single write access time t 220 note (1 + t0 + t1 w + t2 w ) ? tf ? 3  (2 + t0 + t1 w + t2 w ) ? tf + 3 ns delay time from advz rise to write signal output t 221 rising edge of ab0_wrz t0tf ? 3  t0 ? tf + 3 ns write signal active width t 222 ab0_wrz = low t1 w ? tf ? 3  t1 w ? tf + 3 ns delay time from wrz rise to csz fall output t 223 rising edge of ab0_wrz t2 w ? tf ? 3  t2 w ? tf + 3 ns asynchronous _wdata output hold time t 224 rising edge of ab0_wrz t2 w ? tf ? 8   ns delay time from address determination to wrz fall t 225 falling edge of ab0_wrz note (1 + t0) ? tf ? 8   ns delay time from csz fall to wrz fall output t 226 falling edge of ab0_wrz note (1 + t0) ? tf ? 3   ns note the time from the csb falling edge to the adv fa lling edge (tf) can be shortened by setting a register. remark tf = 1/4 of ab0_clk. (when frequency ratio 1/4 is us ually the time of the state (ab0_clk:flash_clk = 2:1). t0, t1, t2, csint: values set to read the wa it timing control register (ab0_csxwaitctrl) t1 w , t2 w : values set to write the wait timing control register (ab0_csxwaitctrl_w)
mc-10118b data sheet r19ds0008ej0700 42 figure 2-8. asynchronous single read timing csz[3:0] benz[1:0] a b0_rdz t 204 a b0_a[25:1] a b0_d[15:0] t 202 t 209 ((lower add) (data) t 205 t 207 a b0_adv t 206 t 208 add t 203 t 201 t 210 t 211 t 212 figure 2-9. asynchronous single write timing csz[3:0] a b0_wrz a b0_a[25:1] a b0_d[15:0] t 202 (lower add) (data) t 223 a b0_adv t 222 t 208 add t 221 t 224 benz[1:0] t 220 t 204 t 225 t 226
mc-10118b data sheet r19ds0008ej0700 43 2.5.4 uart interface (io buffer drive capability: 2 ma) parameter symbol conditions min. typ. max. unit uartx_sout output delay time t dc falling edge of uartx_ctsb   4 rclk uartx_rtsb output delay time t dr center of uartx_srin stop bit   3 rclk remark rclk: 1/16 of baud rate clock cycle figure 2-10. uart interface timing uartx_sout uartx_ctsb stop data start t dc uartx_srin uartx_rstb stop data start t dr remark x = 0 to 2 (uartx_ctsb and uartx_rstb for ua rt0 and uart2 are pins and are not provided for uart1.)
mc-10118b data sheet r19ds0008ej0700 44 2.5.5 iic interface (io buffer drive capability: 2 ma) standard mode note 1 high-speed mode note 1 parameter symbol conditions min. max. min. max. unit iic_scl clock frequency f c  0 70 0 341 khz iic bus free time t bf interval between stop and start conditions 4.7 ? 1.3 ? ? s iic hold time note 2 t h1  4.0 ? 0.6 ? ? s t wl ?low? state 4.7 ? 1.3 ? ? s iic hold time (scl clock) t wh ?hi? state 4.0 ? 0.6 ? ? s iic setup time t su1 start condition restart condition 4.7 ? 0.6 ? ? s iic data setup time t su2  250 ? 100 note 3 ? ns iic rise time t r sda and scl signals ? ? ? 300 note 4 ns iic fall time t f sda and scl signals ? ? ? 300 note 4 ns iic setup time t su3 stop condition 4.0 ? 0.6 ? ? s clock fall output 5.0 ?  ? ? s iic data hold time t h2 clock fall input 0 3.45 0 note 5 0.9 note 6 ? s capacitance load of each iic bus line c b  ? 400 ? 400 pf notes 1. select the standard mode or high-speed mode by using the smc0 bit of the iic0 clock select register (iiccl0). 2. at the start condition, the first clo ck pulse is generated after the hold time. 3. the high-speed mode i 2 c bus can be used in the standard-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the iic _scl signal?s low state hold time: t su2 ? 250 ns 4. do not input noise exceeding the hy steresis width of the 1.8 v system io schmitt buffer during a rise or fall time. 5. the system requires a minimum of 300 ns hold time internally for the sda signal (at v ih (min.) [0.7 v dd2 ] of iic_scl signal) in order to occupy t he undefined area at the falling edge of iic_scl. 6. if the system does not extend t he iic_scl signal low hold time (t wl ), only the maximum data hold time (t h2 ) needs to be satisfied.
mc-10118b data sheet r19ds0008ej0700 45 figure 2-11. iic bus interface timing iic_scl iic_sda t bf t h2 t su2 t h1 t wl t r t f t wh t su1 t h1 t su3 stop condition start condition stop condition restart condition iic_scl iic_sda
mc-10118b data sheet r19ds0008ej0700 46 2.5.6 audio/voice interface (1) slave mode parameter symbol conditions min. typ. max. unit pmx_clk cycle time t c  100   ns pmx_clk high-level width t wh  40   ns pmx_clk low-level width t wl  40   ns clock rise time t r    10 ns clock fall time t f    10 ns pmx_si, pmx_sen setup time t su rising and falling edges of pmx_clk 20   ns pmx_si, pmx_sen hold time t h rising and falling edges of pmx_clk 20   ns pmx_so output delay time t d rising and falling edges of pmx_clk 0  20 ns remark time from the valid edge x = 0, 1 figure 2-12. audio/voice interface timing (slave mode) pmx_clk (input) t c t wh t wl t su t h t d pmx_si (input) pmx_sen (input) pmx_so (output) t r t f
mc-10118b data sheet r19ds0008ej0700 47 (2) master mode parameter symbol conditions min. typ. max. unit pm0_clk cycle time t c  100   ns pm0_clk high-level width t wh  40   ns pm0_clk low-level width t wl  40   ns clock rise time t r    10 ns clock fall time t f    10 ns pmx_si setup time t su  20   ns pm0_si hold time t h  20   ns pm0_so, pm0_sen output delay time t d  ?5  20 ns remark time from the valid edge x = 0, 1 figure 2-13. audio/voice interface timing (master mode) pmx_clk (output) t c t h t l t su t h t d pmx_si (input) pmx_so (output) pmx_sen (output) t r t f
mc-10118b data sheet r19ds0008ej0700 48 2.5.7 sdio interface sd0 (sdia), sd1 (sdib), sd2 (sdic) parameter symbol conditions min. typ. max. unit clock cycle t cyc  24.0   ns output clock high-level width t hwcko  11.5   ns output clock low-level width t lwcko  11.5   ns output delay t od    2 ns input clock high-level width t hwcki  7.5   ns input clock low-level width t lwcki  7.5   ns input clock delay time t dcki    6 ns setup time t iscki  3.5   ns hold time t ihcki  0   ns figure 2-14. sdio interface timing sdx_cko (output) t cyc t hwcko t lwcko t od sdx_data[3:0] (output) sdx_cmd (output) sdx_cki (input) t cy c t hwcki t lwcki t i sck i t ihcki t dcki sdx_data[3:0] (input) sdx_cmd (input) remark x = 0 to 2
mc-10118b data sheet r19ds0008ej0700 49 2.5.8 camera interface parameter symbol conditions min. typ. max. unit cam_clki input cycle t c  12.5   ns cam_clki high-level width t wh  4   ns cam_clki low-level width t wl  4   ns cam_yuv[7:0], cam_hs, cam_vs setup time t su0 det = 0 5   ns cam_yuv[7:0], cam_hs, cam_vs hold time t h0 det = 0 0   ns cam_yuv[7:0], cam_hs, cam_vs setup time t su1 det = 1 5   ns cam_yuv[7:0], cam_hs, cam_vs hold time t h1 det = 1 1   ns figure 2-15. camera interface timing cam_clki (input) t c t wh t wl t su 0 t h0 det = 0 cam_yuv[7:0] (input) cam_hs, cam_vs (input) t su1 t h1 det = 1 cam_yuv[7:0] (input) cam_hs, cam_vs (input)
mc-10118b data sheet r19ds0008ej0700 50 2.5.9 lcd interface parameter symbol conditions min. typ. max. unit lcd_pxclk cycle t c  30   ns lcd_pxclk high-level width t wh  12   ns lcd_pxclk low-level width t wl  12   ns lcd_pxclk rise time t r 20 to 80%   5 ns lcd_pxclk fall time t f 80 to 20%   5 ns t d1 lcd_r[5:0], lcd_g[5:0], lcd_b[5:0] 0  10 ns data delay time t d2 lcd_vsync, cd_hsync, lcd_enable 0  10 ns remark the setting of the rise and fall timing for lcd_ pxclk is based on the valid edge set by the clkpol value in the lcd control register (risi ng: clkpol = 0, falling: clkpol = 1). figure 2-16. lcd interface timing lcd_pxclk t c t wh t wl t d2 lcd_r[5:0] lcd_g[5:0] lcd_b[5:0] lcd_enable lcd_hsync lcd_vsync t r t f t d1
mc-10118b data sheet r19ds0008ej0700 51 2.5.10 usb interface parameter symbol conditions min. typ. max. unit usb_clk cycle t k01 60 mhz  16.7  ns usb_clk high-level width t k02  7   ns usb_clk low-level width t k03  7   ns usb_clk rise time t k04    2 ns usb_clk fall time t k05    2 ns usb control input setup time t k06  5   ns usb control input hold time t k07  1   ns usb data input setup time t k08  5   ns usb data input hold time t k09  1   ns usb data output delay time t k11  0.5  7 ns usb_stp output delay time t k10  1  9 ns figure 2-17. usb interface timing usb_clk (input) t k0 1 t k02 t k03 t k08 t k0 9 usb_data[7:0] (output) usb_data[7:0] (input) t k0 4 t k0 5 usb_stp (output) t k06 t k0 7 t k10 usb_dir (input) usb_nxt (input) t k11
mc-10118b data sheet r19ds0008ej0700 52 2.5.11 spi interface (1) master mode parameter symbol conditions min. typ. max. unit common to sp0, sp1, and sp2 spx_clk output cycle t c  40   ns spx_clk high-level width t wh  16   ns spx_clk low-level width t wl  16   ns spx_clk rise time t r 20 to 80%  4 ns spx_clk fall time t f 80 to 20%  4 ns sp0 sp0_si setup time t su0 rising and falling edges of sp0_clk 12   ns sp0_si hold time t h0 rising and falling edges of sp0_clk 0   ns sp0_so delay time t do0 rising and falling edges of sp0_clk 0  12 ns sp1 sp1_si setup time t su1 rising and falling edges of sp1_clk 12   ns sp1_si hold time t h1 rising and falling edges of sp1_clk 0   ns sp1_so delay time t do1 rising and falling edges of sp1_clk 0  12 ns sp2 sp2_si setup time t su2 rising and falling edges of sp2_clk 12   ns sp2_si hold time t h2 rising and falling edges of sp2_clk 0   ns sp2_so delay time t do2 rising and falling edges of sp2_clk 0  12 ns
mc-10118b data sheet r19ds0008ej0700 53 figure 2-18. spi interface timing (master mode) spx_clk (output) t c t wh t wl t do spx_so (output) t r t f t su t h spx_si spx_csn (input) remarks 1. the level of the spx_clk output can be inverted by setting a register. 2. spx_clk is not output while spx_clk is inactive. (fixed to inactive.) 3. if the read latency of the connect ed device is long, the time can be adjusted by means such as using a function to switch the i/o phase of si and so (by using the rise and fall of sclk).
mc-10118b data sheet r19ds0008ej0700 54 (2) slave mode parameter symbol conditions min. typ. max. unit common to sp0, sp1, sp2 spx_clk input cycle t c  50   ns spx_clk high-level width t wh  20   ns spx_clk low-level width t wl  20   ns spx_clk rise time t r    4 ns spx_clk fall time t f    4 ns sp0 sp0_cs setup time t su0 rising and falling edges of sp0_clk 5   ns sp0_cs hold time t h0 rising and falling edges of sp0_clk 15   ns sp0_so delay time t do0 rising and falling edges of sp0_clk 3  18 ns sp1 sp1_cs setup time t su1 rising and falling edges of sp1_clk 5   ns sp1_cs hold time t h1 rising and falling edges of sp1_clk 15   ns sp1_so delay time t do1 rising and falling edges of sp1_clk 3  20 ns sp2 sp2_cs setup time t su2 rising and falling edges of sp2_clk 5   ns sp2_cs hold time t h2 rising and falling edges of sp2_clk 15   ns sp2_so delay time t do2 rising and falling edges of sp2_clk 3  18 ns figure 2-19. spi interface timing (slave mode) spx_clk (input) t c t wh t wl t do spx_so (output) t r t f t su t h spx_si spx_csn (input)
mc-10118b data sheet r19ds0008ej0700 55 2.5.12 dtv interface parameter symbol conditions min. typ. max. unit dtv_bclk input cycle t c  66   ns dtv_bclk high-level width t wh  28   ns dtv_bclk low-level width t wl  28   ns dtv_data, dtv_psync, dtv_vld setup time t su  12   ns dtv_data, dtv_psync, dtv_vld hold time t h  12   ns figure 2-20. dtv interface timing dtv_bclk (input) t c t wh t wl t su t h dtv_data[7:0] (input) dtv_psync (input) dtv_vld (input)
mc-10118b data sheet r19ds0008ej0700 56 2.5.13 nand flash interface parameter symbol conditions min. typ. max. unit cle setup time t cls  t c-3  8 t c+3 ns cle hold time t clh  t c-3  8 t c+3 ns ale setup time t als  t c-3  8 t c+3 ns ale hold time t alh  t c-3  8 t c+3 ns write pulse width t wp  t c-3  16 t c+3 ns wez high-level hold time t wh  t c-3  16 t c+3 ns write data setup time t ds1 rising edge of nand_wez t wp-3  t wp+3 ns write data hold time t dh1 rising edge of nand_wez t wh-3  t wh+3 ns remarks 1. t c = t c (ahb) in the above table 2. the ac characteristics for nand_wez, rez, cl e, and ale are determined by a register setting, and the unit is t c (when ahb = 83 mhz with acpu operating at 500 mhz). figure 2-21. nand flash interface timing 1 n and_ cl e (o u t p u t ) n and_ale (output) n and_we (output) n and_da (output) t cls t clh t wp t ds1 t dh1 t wp t wh t al s t alh t ds1 t dh1 t ds1 t dh1 t wp
mc-10118b data sheet r19ds0008ej0700 57 parameter symbol conditions min. typ. max. unit read pulse width t rp  t c-3  16 t c+3 ns high-level hold time t reh  t c-3  16 t c+3 ns read data setup time t ds2 rising edge of nand_oe 8   ns read data hold time t dh2 rising edge of nand_oe 0   ns remarks 1. t c in the above table = t c when ahb = 83 mhz with acpu operating at 500 mhz, = 12 ns 2. the ac characteristics for nand_we, oe, cle, and ale are determined by a register setting, and the unit is t c . 3. the internal bus clock is used for data latching during reading via nand_da (input). figure 2-22. nand flash interface timing 2 nand_oe (output) nand_da (input) t rp t reh t ds2 t dh2
mc-10118b data sheet r19ds0008ej0700 58 2.5.14 itu-r bt.656 interface parameter symbol conditions min. typ. max. unit ntsc_clk input cycle t c   37 note  ns ntsc_clk high-level width t wh  13   ns ntsc_clk low-level width t wl  13   ns ntsc_clk rise time t r   5 ns ntsc_clk fall time t f   5 ns ntsc_data output delay time t d rising edge of ntsc_clk 4  18 ns note ntsc_clk = 27 mhz figure 2-23. itu-r bt.656 interface timing nts_bclk input t c t wh t wl t r t d nt s_data[7: 0] output nts_vs (output) nt s_hs output t f
mc-10118b data sheet r19ds0008ej0700 59 2.5.15 microwire interface parameter symbol conditions min. typ. max. unit mwi_sk clock cycle t c  160   ns mwi_sk clock high-level width t wh  72   ns mwi_sk clock low-level width t wl  72   ns mwi_sk clock rise time t r    8 ns mwi_sk clock fall time t f    8 ns mwi_si setup time t su rising edge of mwi_sk 20   ns mwi_si hold time t h rising edge of mwi_sk 0   ns mwi_so, mwi_csn output delay time t d rising edge of mwi_sk   20 ns figure 2-24. microwire interface timing mwi_sk (output) t c t wh t su mwi_si (input) mwi_so (output) mwi_c s0 (output) mwi_c s1 (output) t wl t r t f t h t d
mc-10118b data sheet r19ds0008ej0700 60 3. package drawing
mc-10118b data sheet r19ds0008ej0700 61 revision history date revision comments february 10, 2009 1.0  april 27, 2009 2.0 incremental update from comments to the 1.0.. june 30, 2009 3.0 incremental update from comments to the 2.0. the item of the power supply start-up sequence is added. (chapter 2.5.16) september 30, 2009 4.0 incremental update from comments to the 3.0. utest pins : handling when not used : leave open -> ?l? level hold. power supply start-up (chapter 2.5.17) s equence is indicated on a user's manual (one chip). december 22, 2009 5.0 incremental update from comments to the 4.0. the specification of the self refresh current is changed with name of product change (mc-10118a->, mc-10118b). february 15, 2010 6.0 incremental update from comments to the 5.0. change in the product name (mc-10118a/b->, mc-10118). a self-refresh electric current was returned to the value of revision 4.0. march 31, 2010 7.0 order name change (mc-10118af1-eny-a -> MC-10118BF1-ENY-A). the specification of the self refresh current is changed with name of product change (mc-10118->, mc-10118b).
data sheet s19657ej6v0ds 62 notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc., the dev ice may malfunction. take care to prevent chattering noise from entering the device when the i nput level is fixed, and also in the tr ansition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input le vel may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it w ill be an output pin. all handling related to unused pins must be judged separately for each devic e and according to related specifications governing the device. (3) precaution against esd: a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. step s must be taken to stop generation of static electr icity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. se miconductor devices must be stored and transported in an anti-static container, static shielding bag or conducti ve material. all test and measurement tools including work benches and floors should be gr ounded. the operator shoul d be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. sim ilar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily def ine the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset oper ation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power s upply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences ma y result in the application of an overvoltage to the internal element s of the device, causing malfuncti on and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related spec ifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current inje ction that results from input of such a signal or i/o pull-up power supply may cause malfunc tion and the abnormal current that passe s in the device at this time may cause degradation of internal el ements. input of signals during the power off state must be judged separately for each device and according to re lated specifications governing the device.
data sheet r19ds0008ej0700 63 the names of other companies and products are th e registered trademarks or trademarks of these companies . ? the information in this document is current as of ma rch, 2010. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specif ications of nec electronics products. not all products and/or types are available in every country. please check with an nec electroni cs sales representative for availability and additional information. ? no part of this document may be c opied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. ? nec electronics does not assume any liability for infri ngement of patents, copyri ghts or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. ? descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operat ion and application examples. the in corporation of these circuits, software and information in the design of a customer 's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility fo r any losses incurred by customers or third parties arising from the use of these circ uits, software and information. ? while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (incl uding death) to persons aris ing from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. ? nec electronics products are classified into the fo llowing three quality grades: "standard", "special" and "specific". the "specific" qua lity grade applies only to nec electronics products developed based on a customer-designated "quality assuranc e program" for a specific applicati on. the recommended applications of an nec electronics product depend on its quality grade, as i ndicated below. customer s must check the quality grade of each nec electronics product before usi ng it in a particular application. "standard": computers, office equipment, communica tions equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (aut omobiles, trains, ships, etc.), traf fic control systems, anti-disaster systems, anti-crime systems, sa fety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor c ontrol systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics pr oducts is "standard" unless otherwi se expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sa les representative in advance to determine nec electronics' willingness to support a given application. (note 1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (note 2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). (m8e0909e)
nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010-8235-1155 http://www.cn.necel.com/ shanghai branch room 2509-2510, bank of china tower, 200 yincheng road central, pudong new area, shanghai, p.r.china p.c:200120 tel:021-5888-5400 http://www.cn.necel.com/ shenzhen branch unit 01, 39/f, excellence times square building, no. 4068 yi tian road, futian district, shenzhen, p.r.china p.c:518048 tel:0755-8282-9800 http://www.cn.necel.com/ nec electronics hong kong ltd. unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: 2886-9318 http://www.hk.necel.com/ nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-8175-9600 http://www.tw.necel.com/ nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 http://www.sg.necel.com/ nec electronics korea ltd. 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 http://www.kr.necel.com/ for further information, please contact: g0706 [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211-65030 http://www.eu.necel.com/ hanover office podbielskistrasse 166 b 30177 hannover tel: 0 511 33 40 2-0 munich office werner-eckert-strasse 9 81829 mnchen tel: 0 89 92 10 03-0 stuttgart office industriestrasse 3 70565 stuttgart tel: 0 711 99 01 0-0 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133 succursale fran?aise 9, rue paul dautier, b.p. 52 78142 velizy-villacoublay cdex france tel: 01-3067-5800 sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 638 72 00 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands steijgerweg 6 5616 hs eindhoven the netherlands tel: 040 265 40 10


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